1. Field of the Invention
This invention concerns a semiconductor device having a substrate bias generator.
2. Description of the Prior Art
Conventionally, a substrate bias generator is widely used. In a dynamic RAM device, the substrate bias generator has important roles, such as the prevention of memory cell errors due to an undershoot of an input signal and the reduction of the capacitance formed by the PN junction in the substrate.
FIG. 1 is a schematic cross sectional view of a conventional semiconductor device which includes an enhancement type dynamic MOS memory cell transistor and a substrate bias generator. Numeral 1 designates a semiconductor substrate of N-type, numeral 2 is a P-type well region, and numeral 3 is an element isolation region. A gate oxide layer 4, a gate electrode 5 made of, e.g., polycrystalline silicon, N-type source region 6 and drain region 7, an N type diffused region 8 and capacitor plate electrode 10 formed on a capacitor insulation layer 9 constitute a dynamic MOS memory cell transistor. BL is a bit line connected to the source region 6.
In the well region 2, another MOS transistor is formed. Namely, a source region 12 and a drain region 13 and a gate electrode 14 formed on a gate oxide layer 15 constitute other MOS transistor. The source region 12 is supplied with the ground potential. The P-type well region 2 is biased by a substrate bias generator 11.
FIG. 2 shows an example of the substrate generator 11. Namely, the bias generator 11 includes a ring oscillator 20, an inverter 27, two capacitors 21, 22, two MOS transistors 23, 24 and two diodes 25 and 26. The common connection of the two MOS transistors 23 and 24 is supplied with the ground potential, and the anodes of the two diodes 25 and 26 are connected to the well region 2 to supply a predetermined bias voltage. Since, the operation of the substrate bias generator 11 is well known, the description thereof is omitted. The bias generator 11 generates a predetermined voltage which is lower than a ground potential, and supplies the potential to the well region 2.
If the integration of a dynamic RAM memory device is increased, and MOS transistors having gate lengths of less than 1 micron are used, the substrate current Isub is significantly increased due to impact ionization. Furthermore, due to high integration, the impurity concentration is increased according to the scaling rule. As an example, the impurity concentration of the well region 2 may be 6.times.10.sup.16 cm.sup.-3, according to the scaling rule.
FIG. 3 shows a relationship between an operation current Icc and the power source voltage. Namely, by gradually raising the power source voltage Vcc, the operating current gradually increases. When the power source voltage Vcc reaches a voltage Vin, the current Icc suddenly increases, and goes to point E from point D.
On the other hand, when the power source voltage Vcc drops to Vout, the current Icc suddenly reduces and goes to point G from point F. In other words, the device has a hysteresis characteristic with respect to the power source voltage. The condition between the point E and F is an error operation area of the device, and the large current raises the temperature of the device.
Referring now to FIG. 4, the mechanism of the hysteresis characteristic will be explained. FIG. 4 shows a dependence of the substrate voltage Vsub on the power source voltage Vcc.
When the power source voltage Vcc reaches the Vin, the substrate current Isub equals the pumping capacity Ibb of the substrate bias generator 11, namely the current Ibb pumped by the substrate bias generator 11. If the power source voltage Vcc exceeds the Vin, the substrate current Isub becomes larger than the Ibb (Ibb&lt;Isub). In this condition, the excess current flows to the ground through the N.sup.+ source region 12 supplied with the ground potential. Thus, the potential of the well region 2 becomes the built-in potential .PHI.B, and the PN junction formed between the well region 2 and the N.sup.+ region 12 formed in the substrate is forward biased. In this condition, since the substrate voltage is raised, the threshold voltage of the N-channel MOS transistors is lowered due to the back gate bias effect.
FIG. 5 shows a relationship between the impurity concentration of the well region and the threshold voltage of the N-type enhancement MOS transistor. The line I in FIG. 5 illustrates a characteristic of an enhancement MOS transistor which is formed in a well region of 6.0.times.10.sup.16 cm.sup.-3 impurity concentration.
As shown by the line I of FIG. 5, the threshold voltage of the enhancement MOS transistor becomes negative when the substrate voltage becomes the built-in potential .PHI.B. Thus, it is presumed that the change of the enhancement MOS transistor to the depletion mode causes the prescribed rapid increase of the substrate current Isub.
At the same time, the substrate current is also increased due to impact ionization occurring at an increasing tempo. Thus, even if the power source voltage is lowered, the operation current Icc does not decrease to the point positioned on the original characteristic curve, but to the point F, as previously explained referring FIG. 3.
The phenomenon that the substrate current Isub exceeds the pumping capacity Ibb of the substrate generator sometimes occurs at the initial precharge of the bit lines and the capacitor plate electrodes of the memory cell transistors after the power source supply.
Since the pumping capacity of the substrate bias generator is in proportion to the capacitance of the capacitors 21 and 22, the capacitance off the capacitors may be increased to prevent the erroneous operation due to the substrate current. However, a large capacitance requires a large area for the capacitor, and this is unfavorable for the integration of the device.